A Complete Platform for RISC-V Design Space Exploration

The Trireme Platform includes everything you need to bring up the hardware and software of a custom RISC-V system, from ultra-low-power microcontrollers to high-performance multi-core processors.

Tools to get You From RTL to "Hello World!"

Trireme Full Toolchain

Multiple output binary formats for use on Linux, bare-metal FPGA systems, or RTL simulations.

Simple parameters to customize binary entry point, stack address & size, heap size, and more. Board Support Package (BSP) included.

Get the Toolchain on Github ⇨

Trireme RTL Modules

Written in Verilog 2001 with fully parameterized modules without any vendor-specific or 3rd party IP.

Build custom hardware systems with a variety of cores, coherent cache configurations, memory modules, and network-on-chip support.

Get the RTL on Github ⇨

Trireme ISA Simulator

Simulate RISC-V ISA instructions right in your browser. Ideal for beginners and classroom use.

Upload C and assembly, or write it in the editor window. Observe register and memory state after each instruction.

Try the Simulator ⇨

Trireme Block Designer

Generate Verilog for a custom core, cache, memory & NoC configuration. Download customized top module.

Select Verilog parameters in a GUI. See a visualization of the configured RISC-V system. Save and export settings for sharing.

Try the Explorer ⇨

Example Systems

From low-power microcontrollers, to Linux ready multi-core processors, the Trireme Platform can do it all. Get started with some of the Trireme Platform's included example systems. The Basin and Cove processor systems are available now to download while we are finishing the release of the Arroyo and Delta processor systems.

Arroyo Processor

Linux ready single-core system

Basin Processor

Dual-core with DRAM or Flash

Cove Processor

Microcontroller with privilege modes

Delta Processor

Simple Out-of-Order core system

Download Links

Download Zip files here or check out the Trireme Platform on Github

Trireme Platform

The complete platform download
Hardware + Software

Download Platform

Hardware (RTL) Code

Every Hardware Module
in the Trireme Platform

Download RTL

Software Toolchain

The complete Development
Software Environment

Download Software

Web-Based Utilities

Browser-Based Software
Debugging

Trireme Simulator

The Trireme Platform in Publications

  • X. Wang, B. Williams, J. D. Leidel, A. Ehret, M. Mark, M. A. Kinsy and Y. Chen: "xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing", In the 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2021.

  • S. Bandara and M. A. Kinsy: "Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks". Journal of Cryptographic Engineering, Springer, 2020.

  • A. Ehret, K. M. Gettings, B. R. Jordan Jr. and M. A. Kinsy: "A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices". In the 2020 IEEE High Performance Extreme Computing Conference (HPEC), 2020.

  • R. Agrawal, S. Bandara, A. Ehret, M. Isakov, M. Mark, and M. A. Kinsy: "The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture", In Workshop on Computer Architecture Education (WCAE), 2019.

  • D. Kava, S. Bandara, M. A. Kinsy: "Architecture Design Space Exploration Using RISC-V". In the Inaugural RISC-V Summit Proceedings (RISC-V Summit), December 2018.

  • Citing The Trireme Platform

    If you use the Trireme Platform in your research, we would appreciate the following citation in any publications to which it has contributed:

    Sahan Bandara, Alan Ehret, Donato Kava and Michel A. Kinsy: "BRISC-V: Open Source Architectural Design Space Exploration Toolbox" Tech-Report 0V1, October 2018.

Authors

The Trireme platform is managed and maintained by the Secure, Trusted, and Assured Microelectronics (STAM) Center in Ira A. Fulton Schools of Engineering at Arizona State University and the Secure Micro Technologies hardware team. Sincere thanks to all the team members who have contributed to the platform.